Electrostatic discharge (ESD) is a phenomenon wherein static build-up, such as produced by friction, is applied to an object. When the object is an integrated circuit (IC) portions of the device can be permanently damaged. Since ESD can involve pulses of many thousands of volts the damage, which often involves the discharge of a capacitance of many tens of picofarads, can be surprisingly high. In testing the tolerance of an IC to ESD it is common to charge a 150 pF capacitor to a controlled variable voltage (typically 1 to 2 kilovolts) and then connect it through a 1.5k ohm resistor to the various pins of the IC. The signal input/output pins are typically the most sensitive to damage from ESD. The capacitor charge is incremented until damage occurs and the level noted. The ESD resistance can then be rated in terms of the highest value of charge voltage that the IC can withstand without harm.
With respect to what can happen when damage occurs, several failure mechanisms can develop. The discharge energy can melt the silicon into which the IC is fabricated. It can also rupture the silicon dioxide insulation. Here it is most likely that a metal oxide semiconductor (MOS) transistor gate oxide rupture will occur first because this oxide is the thinnest in the IC. Further, it can cause fusion of the aluminum interconnect metal or evaporate polysilicon conductors. The above actions usually destroy the IC. However, at lower ESD levels PN junctions can be degraded so that leakage currents can increase to an unacceptable level. Accordingly, the ESD limits are related to acceptable performance levels.
FIG. 1 shows a protected complementary MOS (CMOS) gate or NOT circuit. Such a circuit is commonly found in the commercial 74HC device series. The gate 9 operates from supply terminals 10 and 11 which respectively represent +V.sub.CC and ground. A signal applied to input terminal 12 appears inverted at output terminal 13. P channel transistor 14 in connection with N channel transistor 15 forms a CMOS invertor. The gates of transistors 14 and 15 are protected by elements 16-22. Resistor 16 is ordinarily a poly silicon resistance having a typical value of about 200 ohms. Diode 17 forms a clamp and conducts when input terminal 12 is force one diode drop above the potential on the +V.sub.CC line. Thus, assuming a 5-volt V.sub.CC, diode 17 will clamp the right hand end of resistor 16 at about 5.6 volts (at 300.degree. K.). Resistor 18 is actually a diffused resistor that forms the cathode of diode 19. Diode 19 will conduct and clamp the input gates when terminal 12 is forced one diode drop below ground. Thus, the gates are also clamped at about -0.6 volt (at 300.degree. K.).
The above clamp levels are sufficiently low that the gates of transistors 14 and 15 are fully protected.
Elements 20-22 provide the protection associated with output terminal 13. When output terminal 13 is forced one diode drop above the potential of the +V.sub.CC line diode 20 will conduct and clamp the output. When terminal 13 is forced to one diode drop below ground diode 21 wil conduct and clamp the swing at about -0.6 volt (at 300.degree. K.). Diode 22 is present to clamp the application of reverse potential between terminals 10 and 11. It will conduct when the reverse potential exceeds about 0.6 volt (at 300.degree. K.).
In the normal circuit operation the applied potentials will reverse bias diodes 17, 19 and 20-22. In this state the shunting produced by the diodes is negligible. The circuit of FIG. 1 will protect against ESD to over 2,000 volts using the above-described test.
Another well known gate protection circuit is found in Borror et al. reissue U.S. Pat. No. 27,972. In the embodiments disclosed a P channel transistor is employed to protect an operating P channel transistor. Accordingly, a -V.sub.DD supply is employed with the + supply terminal at ground. In one embodiment (FIG. 1) a conventional FET is coupled as a series resistor between the input terminal and the protected gate. The diode formed by the FET source appears across the input terminal to ground. The gate of this device is connected to V.sub.DD so that it is normally biased heavily on and will thus act as a relatively low value resistor. When the input terminal is forced one diode below ground, the FET related diode will clamp. When the input terminal is forced to within one threshold voltage above V.sub.DD the transistor will be turned off so as to disconnect the input from the protected gate.
In the second embodiment (FIG. 2) a shunt FET is employed with a series connected dropping resistor. The shunt FET employs a thick gate oxide and its drain is connected to its gate. Such a structure will have a threshold voltage that is higher than that of the protected MOS transistor (which has a thin oxide), but the threshold will still be much lower than the thin oxide rupture voltage. Therefore, when a high voltage is applied to the input terminal, the thick oxide FET will turn on and conduct and the voltage will be dropped across the series resistor. Under the normal circuit operation the thick oxide FET will be nonconductive and will thus have no effect.
As can be seen in the above prior art examples, the clamping potentials are not symmetrical. This condition is aggravated when a bias voltage is present at the supply terminals. It would be desirable to provide a protection circuit that is symmetrical and unrelated to the supply voltage.